| | | 20,000+ Fresh Resumes Monthly | |
|
|
| |
Click here or scroll down to respond to this candidate Candidate's Name
Mask Design Engineer 2.5 years experience
EMAIL AVAILABLE | PHONE NUMBER AVAILABLE | San Jose CA | LINKEDIN LINK AVAILABLE
OBJECTIVE
Seeking a Graduate Technical Intern/Full time position in Hardware domain.
EDUCATION
MS in Electrical Engineering VLSI Design, San Jose State University GPA: 3.50 Expected
May16
BS in Electronics Engineering, Visvesvaraya Technological University, India GPA: 3.82
July11
TECHNICAL SKILLS
Languages: Verilog, VHDL, C, Python
Technical Tools: Cadence (Spectre, Spectre RF, Ultrasim, Analog Artist, Virtuoso, ADE L, ADE XL,
Schematic and Layout Editor), Encounter, Synopsys IC Compiler & Primetime, Calibre/Assura DRC,
Hercules/Assura LVS, Synopsys VCS, Design Vision, ModelSIM, MATLAB Simulink.
RELEVANT WORK EXPERIENCE
Mask Design Engineer I SanDisk Corporation, India Oct12
July14
Designed layouts for Digital, Analog and I/O blocks to fit the given area and gained proficiency in NAND Design
Flow and methodology, Power/IR/EM analysis, Debugging DRC/LVS at full chip level and RC extractions.
Solid hands-on experience in Synthesis and Place & Route, Floor-planning, Matching, Layout optimization.
Received 2 awards for exemplary performance in placement and routing of decoupling capacitors for entire region
of IO PADS and fixing ESD related DRC and latch up errors.
Led a team of 11 in the Corporate Social Responsibility activities through a NGO DreamADream.
Analog Mixed Signal Layout Engineer Sankalp and KPIT Semiconductors, India Jan12
Oct12
Acquired strong knowledge on ESD, Lithography, EM, DFM, Antenna effects, Netlist-to-GDS flow, Clock Tree
Synthesis, Fabrication challenges and worked on standard cell layouts using GPDK90nm and TSMC45nm.
Proactively created documents on layout design techniques and assisted in training the New College Graduates.
Research Intern Indian Institute of Science, India Jun10
Aug10
Conducted extensive research on Optical Microsensors and its applications in Aerospace.
ACADEMIC PROJECTS
RF Transmitter for Bluetooth Applications - 45nm CMOS Technology
Spring16
Design includes a Frequency Mixer, a Voltage Controlled Oscillator (VCO) and a Power Amplifier.
High FoM Bluetooth Low Noise Amplifier - 45nm CMOS Technology
Fall15
Designed a Bluetooth Low Noise Amplifier and achieved a Figure-of-Merit of 11.6GHz.
Phase Locked Loop (PLL) - 10nm SGFET Technology
Fall15
Designed a PLL to achieve highest possible frequency, lock range and lowest possible power dissipation.
Time to Digital Converter (TDC) - 45nm CMOS Technology
Spring15
Implemented and integrated individual blocks such as voltage controlled ring oscillator, counters, and edge
frequency detectors and tested the working of TDC for all process corners achieved 5ps time resolution.
Micro Opto Electro Mechanical (MOEM) Vibration Sensor
Spring11
Designed a MOEM vibration sensor and achieved a sensitivity of 0.0274pm/g for a g-force of 7302.19g.
OTHER ACTIVITIES
Research Publication: Sudarshan. S. M, et al., Design of MOEM vibration sensor using optical microring
resonator and microcantilever beam, IEEE Region 10 Conference TENCON, 2011, pp. 747-751.
Graduate Technical Assistant, San Jose State University: Troubleshooting technical issues and hardware
problems.
Instructional Student Assistant, San Jose State University: Assisting students for the High Speed CMOS course.
Isha Volunteer: Handled the registration activities in the yoga and meditation program conducted by Isha Yoga
Foundation held in fall15 in the Bay Area.
|
