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PHONE NUMBER AVAILABLE | EMAIL AVAILABLE LINKEDIN LINK AVAILABLE [pic] Hardware & PCB Layout Engineer having over 7 years of R&D experience with complete Product design knowledge, including High Speed PCB Layout, schematic creation, component engineering, simulation, testing, measurements, prototype handling, logistics and documentation fueling quality enhancement of the product.TECHNICAL EXPERTISE:Wireless: Hardware Design & Testing, Complete Product Development LifeCyclePCB Layout: Designing Multilayer Analog, Digital & High Speed BoardsCustomer Products: Hand Held Meter reading instruments CMRI, GPS SyntimeRDU, Calibration Equipments TPRS, SPRS. Static Tri-vector Meter,Multifunction Transducers, Various SOM boards featuring ATMEL, FREESCALEIMX6, CONGATECH, MARVELL ProcessorsOperating Systems Windows XP, Vista / 7 /8 /2008 server.Tools ORCAD, PROTEL 99SE, CADENCE ALLEGRO, MENTOR GRAPHICS-PADS,EXPEDITION, PSPICE, View-mate, SOLIDWORKS, AUTOCADProgramming Languages C, C++Skill Sets EMI/EMC, Library Creation & Handling, Pre & Post gerber Creation& Handling, PCB Assembling, DFM, DFT, Technical Documentation, Handling ECN& CAPA, Measurements using IQXL, Network Analyzer & Signal Analyzer PROFESSIONAL EXPERIENCEMARVELL INDIA Pvt Ltd, Pune, India Dec'14- PresentSr.PCB Layout Engineer, WSH-R&D . Managed a team of 2 engineers. . Handling entire design section starting from schematic, layout and complete product development life cycle . Made High Speed RF Test boards, Debug boards, RD boards using various MARVELL Processors like 88W8987, 88W8887, 88W8897, 88W8997, 88MW300, 88MW302, 88W8777, 88W8977,88W8964 . Involved in complete In-house product development for testing the functionality of the various processors . Products named as 12 Channel Attenuator, Marvell Signal Generator, SC-4 . Handling Marvell Global Library (ACES) along with 4 Design Engineers all over MARVELL Global sites . Involved in various measurement activities in lab like RF 2G, 5G path loss, current, temperature measurements using devices like IQXL, Network analyzer, Signal Generator & Analyzer, Temperature Chamber . Interact with Vendors related to mechanical constraints and requirements of product & PCB Fabricators in pre & post processing of PCB . Currently handling a project named SLATE. This will be a complete product with socket aligned on the board to test millions of Marvell chip for its functionality. This product will be mounted on a robotic tray and movement of robotic arms will handle the equipmentSANDS (INDIA) Pvt Ltd, Chennai, India Feb'10- Nov'14.Sr.R&D Engineer (Project & Development), R&D . Managed a team of 3 engineers. Responsible for monitoring their individual progress, conduct appraisals and fuel continuous learning and implementation of new ideas. . .Handled entire system design starting from timelines, schematic, layout, BOM Generation, component selection, library handling and gerber creation . Interact with Vendors related to mechanical constraints and requirements of product & PCB Fabricators in pre & post processing of PCB . Handled HV ,HC & MEGGER Test for PCB received after fabrication . Handled initial board bring up, stage wise testing and integration testing . Was involved in Manual testing and creation of test cases and executing test cases on products and logging down bugs . Have done more than 50 boards which includes multilayered complex designs and High speed signals . Made high speed RF boards, prototypes and test boards using various processors like Freescale IMX6 SOLOLITE, Congatech Q7, Calixto SOM modules, SBC, ATMEL, MSP430f47196, LPC2364, LPC2378 ARM Processors . Handled products like CMRI, TPRS, SPRS, CMRI-NG, RDU, SYNTIME, MFT- 204, MFT-MBD, STM and various other customer oriented projects . Actively involved in calibration of Test equipments like SPRS, TPRS, MFT & Energy Meter STM . Actively involved in designing mechanical aspects like cabinets and interior box designs for all products . Handled ordering of components for prototypes and also performing various tests like Vibration test at ETDC to make it IEC certified. . Handled ECN & CAPA for all products . Prepared necessary documents and Handled ISO audits for R&D department for the year 2012, 13 & 14VIRYA InfoTech Pvt Ltd. Chennai, India July'09 - Jan'10PCB Layout Engineer, R&D . Handled entire system design starting from timelines, schematic, layout, BOM Generation, component selection, library handling and gerber creation . Interact with Vendors related to mechanical constraints and requirements of product & PCB Fabricators in pre & post processing of PCB. . Made high speed RF boards, prototypes and test boards for customers up to 16 layers EDUCATION & CREDENTIALSBachelor of Engineering (Anna University, Electronics & Communications,2009 Batch): First Class with Distinction (75%)H.S.C (St. Peters Hr Sec School, Chennai): 89%S.S.L.C (St. Peters Hr Sec School, Chennai): 92%Certification from NIIT in 'C' & C++.ACCOLADES from EMPLOYERS: . Spot Award for contribution towards the fast completion of IMX6 CMRI NG Touch screen project. This was given by MD of SANDS (INDIA) . Spot Award for contribution towards the fast completion of customer project. This was given by MD of VIRYA InfoTechTRAINING PROGRAMMES: . In-plant training Program in Sands Instrumentation Pvt Ltd on Microprocessors and Microcontrollers . Attended Various design conferences conducted by Mentor Graphics, Wruth Electronics, Cadence Orcad community, NXP & TI . Attended Training Program on IMX6 Processor Family which was held by Freescale at Bangalore . Attended Training Program which was held by Calixto systems at BangalorePERSONAL INFORMATION: Name : Candidate's Name
Email : EMAIL AVAILABLE Contact Numbers : PHONE NUMBER AVAILABLE PHONE NUMBER AVAILABLE Passport Number: H4786486 LinkedIn id : LINKEDIN LINK AVAILABLE Skype Id : s.arfajecestar Contact address : 23/11 Bazaar street, Royapuram, Chennai- 600013, Tamil Nadu, India Gender : Male DOB : 25/02/1987 Languages Known: English, Hindi and TamilDECLARATION: I hereby declare that all the information provided above are true and best of my knowledge.Date: (Candidate's Name ) |
