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Elevates mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industrys most complex ATE challenges. We strive to exceed our customers expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test.

Responsibilities

• Schematic design and simulation of circuits for a variety of high speed and precision CMOS ATE circuits.
• Layout, verification and post layout simulation of circuits. Include Monte Carlo, SOAC and corner analysis. Mixed signal simulation at channel and chip level.
• Develop innovative circuit architectures to optimize power, performance and density.
• IC characterization and support of test development and qualification for ATE specific parameters and use conditions.

Requirements

• Bachelors degree in Electrical Engineering; Masters degree preferred
• Solid analog CMOS circuit design fundamentals.
• Ability to design and analyze complex feedback loops. Stability analysis and design of compensation schemes.
• Ability to seamlessly interface with internal and external functions (engineering, manufacturing, application, etc.) to develop leading ATE products.
• Understanding of the IC design, qualification and manufacturing cycle.
• Experience with industry standard analog and mixed signal EDA tools. (Cadence/Mentor Graphics/Tanner. LVS and DRC using Cadence or Mentor tools.)