Responsibilities and Duties

 

• Develop block level test plan, UVM test bench components such as agents (drivers/monitors), scoreboard, constrained random testcases based on UVM sequences, assertions.


• Develop and close functional coverage, code coverage.


• Ability to independently execute on test plan, run simulations and debug.

Qualifications and Skills

 

• 7+ years of ASIC verification experience


• UVM/System Verilog


• VCS simulator, Verdi


• 2, 3 projects experience with UVM based testbench, coverage closure