• 10 or more years’ experience in design, implementation and verification of storage and/or networking


• ASICs.


• Strong communication skills, both verbal and written.


• Proficiency with Verilog & System Verilog RTL coding and verification


• Proficiency with UVM strongly desired


• Familiarity with synthesis and static Timing


• Experience with FPGA flows and the Xilinx and/or Altera toolset helpful


• Experience in architecting test bench environments for unit and system level verification


• Protocol knowledge in one or more of the following areas


• TCP/IP, SCSI, Fiber Channel, Ethernet, SAS, SATA, RDMA protocols & PCIe


• Proven track record with writing detailed test plans


• Problem solving skills and out-of-the-box thinking to test and validate RTL

RESPONSIBILITIES

• RTL Design & RTL Verification Micro-architecture & Documentation


• RTL Coding


• RTL Verification – Verification environment, coding and test writing


• System testng and debug using FPGAs


• Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)


• Scriptng


• Test plan documentaton