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Job Description:

• Providing accurate schedules
• Meeting project milestone deadlines
• Full self-sufficiency in debugging complex verification failure
• Mentoring of junior layout designers
• Delivering high quality layout that conforms to all design requirements.
• Full understanding of hierarchical planning (top down and bottom up) and integration
• Chip design from bottom-up planning through tape out Skills:
• Experience in layout Floor-planning, LVS, DRC, ANT, ESD, LU, EMIR and Reliability
• Strong analog layout skills, including matching, signal shielding, and current mirrors
• Ability to provide and maintain layout schedules
• Experience in advanced technology nodes, 20nm and below, and FINFET technologies is required Qualfications
• Undergraduate Degree in engineering

Additional Information:

• Candidate should have the following tool experience:
• Allegro Version 17.4
• Able to work on-site for PCB Team Design effort.
• Expert placement of Power Controllers and delivery of.
• Expert understanding of High-Speed routing and common voiding practices.
• Expert understand of Embedded DDR4 Routing
• Cadence tool Application Mode's
• o Flow Planning
• o Etch
• Extensive use with all the Auto Interactive tools and Timing Vision
• Ability to author and edit layout constraints capturing high speed requirements in Allegro Constraint Manager