We are currently on a hunt for a Lead Project Engineer to join our client's team in Santa Clara, CA.



What you’ll be doing:

• This is a technical position, working closely with verification and ASIC development teams as well as customers. 


• You will lead and drive projects, provide technical leadership, and make sure the team delivers final silicon designs from R&D to the customer. 


• In-Depth knowledge of Design & Verification and be able to provide feedback to the design team.


• Work and liaison with other Design & Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.


• Will be part of a team delivering silicon solutions to some of the biggest brands in the world.

We would love to hear from you if :

• You have 8+ years experience in an SoC Organization.


• You have BS/MS in Computer Science or Electrical Engineering.


• Functional understanding of constrained random verification (UVM), functional coverage, and code coverage.


• Functional understanding of clock domain crossings, lint/cdc checks, SDC, leading protocols such as PCIe, USB, MIPI, experience with embedded CPUs.

PS:Excellent Base Pay + Benefits + Relocation.

We embrace diversity and equal opportunity in a serious way.