Job Description

• Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation.
• Hands on experience in ICC and primetime.
• Block level implementation from netlist to GDS.
• Handling timing closure of high frequency blocks.
• Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level.
• Handling blocks of high instance counts 1M instance and above.
• Understanding constraints and fixing techniques.
• Understanding SI prevention, fixing methodology and implementation.
• Proficient in layout edit techniques.
• Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set.
• Experience in Design Automation and UNIX system.
• Experience in Tcl/ PERL is a plus.

Job Classification

Contact Details: