W-2 CONTRACT ONLY



Job Description

• As a member of QCOM Central EDA team, define and develop solution for physical design flow, SOC integration and PPA optimization of high performance and low power cores.


• The candidate will develop and qualify the Techfiles, methodology and implementation flow in advanced technologies like 10nm and below.


• The candidate will be working closely with Foundries, QCT process team, physical verification team and Physical design team.


• This position requires in-depth understanding of the physical design flow, advanced design rules, DFM, statistical timing closure and reliability analysis.

Minimum Qualifications

• Skills/Experience 3 - 5 years relevant industry experience.


• Good knowledge of SOC design flow, synthesis, PnR/extraction/Timing tools (link removed)>
  
• Expertise in P&R tools from Synopsys and/or Cadence.


• Proficient in understanding design rules/DRM, calibre runs.


• Strong coding skills -Proficient in UNIX and Perl.


• Experience in Makefile, Tcl/Tk, PERL, Python.


• Familiar with multi-voltage design and UPF (link removed)>
  
• Excellent interpersonal and analytical skills with the ability to work independently.


• Highly motivated, excellent team spirit, product and customer oriented.

Preferred Qualifications

• CAD automations skills, Deep expertise in at least one P&R tool, Experience with PD Advanced process nodes

Education

• Required: Bachelor's, Electrical Engineering

Duration

• 1 Year+