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Pre Silicon Functional Validation Engineer
Location: US-CA-San Jose
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• This position will focus more on FPGA pre-Si validation work.
• Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
• 4+ years of experience in the area of either hardware design or verification.
• 2+ years of pre-si verification work using a validation methodology such as UVM, Specman E, VMM, AVM.
• Possess a Bachelor's or Master's degree in Electrical Engineering and/or Computer Engineering and/or Computer Science.

Alois Staffing -USA

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