Job Responsibilities

• Develop block-level and SoC-level micro-architectural designs in SystemVerilog


• Work with the physical design team to facilitate floorplanning, power reduction, and timing closure.


• Implement datapath, control and chip-global features such as power management, clock-domain-crossings, reset, initialization, and DFx (Design for Test, Debug, Manufacturing, Yield, etc)


• Review code coverage and create functional coverage points to contribute to design verification closure.


• Work with software team to ensure high-accuracy mapping from architectural models to hardware implementations

• RTL coding experience with Verilog and System Verilog.


• Experience with RTL for high speed I/O interfaces, compute cores, DFT, and SoC interconnect.


• Track record of successful tapeouts of ASICs of significant scope (size, frequency, power).