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Role :- Senior STA / Physical Design Engineer Location :- Santa Clara, CA & Austin, TX Type :- FTE Job description: Expertise in Synthesis/STA for High Performance , Low Power, Low Area based Flows Expertise in SDC Constraints Creation and constraints cleanup based on the timing issues Expertise in Pre layout and Post layout timing analysis Primetime/Tempus tools Expertise in Running PTSI/ETS tools for Timing Sign-off and generating timing ECO based on the timing issues Expertise in Implementing complex Top/Block level ECO implementation. Good knowledge in Fixing Setup/Hold/Cap Pulse width checks using ECOs Expertise in Complex Full chip Timing analysis and Full chip ECO implementation Expertise in Multi-mode multi-corner STA analysis on SoC Expertise in AOCV/POCV, Clock reconvergence pessimism removal concepts of STA Skill and experience in scripting using TCL/PERL/PHYTHON is highly desirable.
tanishasystems
