Will test, debug, and verify in-house chip design as a member of the verification team; create the Universal Verification Methodology (UVM) testbench that is written in System Verilog to verify the functionality and performance of the chip; examine the interrupt, register access, and Direct Memory Access (DMA) functionality in a full chip simulation with Praveen; verify the detailed feature of a device link controller module with team members; collaborate across company's verification teams to bring up new verification methods and test plans; engage in design-verification cross-team reviews to come out better solution for the hardware bug.
A Master's degree in Electrical Engineering or Electrical Engineering and Computer Science, or Electrical and Computer Engineering, or Computer Engineering, or a related field is required.

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