W-2 CONTRACT ONLY



Job Description

• The work environment is fast paced and dynamic so the candidate should be flexible in their work assignments and task priorities.


• The ability to learn new technical skills and a willingness to adapt to new projects is crucial.


• The candidate will work as part of a team of engineers to develop innovative hardware and SOC solutions technologies for next generation technology platforms.


• Responsibilities include the ability to write, execute and debug tests from test-plans or functional specifications, design and develop verification environment components.


• Verification components to be developed may include bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries.


• Develop test-benches for block level and top-level verification.


• Must be a team player with excellent oral and written communication skills.

Minimum Qualifications

• 2+ years of experience in Design Verification with multiple design cycles in ASIC flow.


• Experience in development of tests based on test-plans or functional specification.


• Experience with verification methodologies like OVM or UVM.


• Design experience using industry-standard hardware description languages (System Verilog)


• Experience in working with Xilinx FPGAs and integrating simulation models for Xilinx IP into the test infrastructure


• Experience in writing test plans and developing the necessary infrastructure for functional verification


• Experience in setting up regressions and debugging test failures


• Experience in Tcl scripting and Perl/Python knowledge for test vector generation and output parsing.

Preferred Qualifications

• Experience in design and development of verification environment components bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries.


• Verification of processors and cache coherent memory systems would be an advantage.


• The candidate should possess knowledge of the state-of-art design-for-verification methodologies and have hands-on working experience in use of verification techniques, tools, and languages.


• Knowledge of SystemC or, C++/OOP and have a strong background in data structures and algorithms is desired.


• Experience in the following tools is desired: Formal Design Verification (Jasper, 0-in, IFV, OneSpin, SLEC, Model Checking); Low-Power Design Verification (UPF, CPF, Power Artist, AVS)


• Scripting languages, preferably Perl, Python, Tcl, etc.

Education

• Required: Bachelor's, Electrical Engineering


• Preferred: Master's, Electrical Engineering

Duration

• 1 Year+