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Verification Engineer
Location: US-CA-San Jose
Jobcode: 59abfded572977acea6b688c9259661f-122020
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- He/She will be responsible to execute development and verification activities individually with/without guidance.
- Experience in developing Testbench for the Block / Cluster / Fullchip and System Level, Testcases, Tesplans and Functional and Code coverage closure activities and reviews of documents and code.
- Fluent in System Verilog HVL and hands-on on Verilog HDL.
- Recent experience in verifying complex control and datapath architectures. CPU/GPU verification experience will be preferred
- Experience on SoC having Basic pipelining, FSMs, Caches
- Hands on experience in developing feature list, testplan and testbench strategies for the DUTs.
- Working knowledge of EDA tools (NCSim,VCS, QuestaSim,IUS)
- Verification of complex RTL design IP / complex FPGA design / SoC at module level and system level.
- Experience in methodology Test Harness, OVM/UVM [Min 3 Years of experience in any of the methodology]
- Experience in any of the protocols like PCIe, Ethernet, USB, NVMe and Memory Controllers, DDRx Families will be advantageous.
Civicminds
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