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Job Title: Formal Verification Engineer

Location: Sunnyvale, CA (Onsite)
Duration: Long term

Job Description:

Complete formal verification for single or multiple design blocks and IP's

• Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
• Proven understanding of formal verification methodologies, complexity reduction techniques and abstraction techniques
• Proven analytical skills to craft novel and creative solutions to tackle industry-level complex designs
• Proven communication skills to ensure effective collaboration with cross functional teams
• Fluency in hardware description languages, such as SystemVerilog and SVA
• Proficiency in scripting languages such as Python, Perl, or Tcl
• Tools: JasperGold or VC-Formal

Thanks & Regards

Nitish Kumar