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Job Description:

Senior DFT engineer with good knowledge of ATPG, JTAG, and MBIST.

ATPG pattern generation and test coverage debugging using Mentor ATPG tools.

Scan and OCC chain insertion using Design Compiler.

RTL and gate-level DFT verifications for DFT logic.

Must Skills:

Scan (Synopsys-DC), ATPG (Mentor Tool), MBIST, Simulations and Silicon Debug

Good to have:

DFT Architecture, iJTAG and IEEE 1500.