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We are looking for a candidate with following Details

Experience:4-6 yrs

Location: Bangalore

Skills required:

• 4+ years experience in design Verification/ worked on SV/UVM
• Must have work exposure in CPU/GPU/DFD or MIPI Protocol
• ASIC/SOC/IP Verification plan definition, testbench environment development in SystemVerilog/UVM
• Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
• Support of assertion and coverage-driven methodology
• Develop test cases to verify the functional operation of that the system level
• Perl, Python, or similar scripting and SW programming language experience
• Good debugging and analytical skills
• Good interpersonal skills & dream to work as a great teammate