Develop fullchip level test plan, Verilog based fullchip testbench components. Familiar with

writing, running and debugging C/C++ based tests. Close Functional/Code coverage. Ability to

independently execute on test plan, run simulations and debug.



Required:

• Verilog knowledge 


• C/C++ coding and debugging


• VCS simulator, Verdi

Desired:

• Previous experience with PCIe, HBM-DDR, Ethernet, SPI, I2C, JTAG, Debug highly desired


• Gate simulation, Power Aware simulation highly desired


• Scripting skills(Perl, Python)


• Emulation experience a plus